The present invention relates to a method for forming small geometry, very dense MOS/CMOS integrated circuits having lightly doped drain/source (LDD) structures and, more particularly, to NMOS and CMOS integrated circuits formed by a process which incorporates sidewall gate oxides and guard band implants in addition to lightly doped drain/source implants without the use of additional photolithographic masking steps.
One of the constant aims of the microelectronics industry has been to achieve ever small device and component dimensions and spacings to provide increased packing densities. However, as the technology has progressed through LSI and VLSI toward future technologies, it has become increasingly difficult to provide the ever smaller, more dense integrated circuit structures and the associated spacings and diffusion depths. Various problems associated with decreased feature size contribute to decreased yields which can offset the savings occasioned by increased packing density and circuit performance. Perhaps chief among these problems are the so-called short channel effects, which include hot carrier injection into the gate oxide and/or substrate, source-to-drain punch through, threshold voltage reduction with channel length and drain/source operating voltage, subthreshold leakage, and impact ionization. For example, in hot carrier injection, electrons are injected into the gate oxide by the high electric field created by the narrow channel region and adjacent the drain and, as a consequence, alter the threshold voltage of the device. In addition to the short channel effects, overlap between the gate electrode and the source and drain diffusions results in parasitic capacitance between the diffusion regions and the gate, known as Miller capacitance, which decrease the device operational speeds.
Another problem encountered in manufacturing small geometry MOS devices relates to electrical shorts between interconnecting conductors such as the electrical conductors contacting the self-aligned gate, source and drain. In the fabrication of silicon gate MOS devices, after forming the polysilicon gate structure and the self-aligned source-drain regions, a metal such as tungsten can be selectively deposited over the polysilicon gate and the source/drain regions to provide low resistance conductor lines. However, the metal deposited in this manner invariably covers the top and sides of the polysilicon gate and can short to the metal deposited over the adjacent source/drain regions. Shorting can also occur between other conductors such as polysilicon interconnect lines.
The above-mentioned hot electron carrier injection, low voltage breakdown and impact ionization problems are alleviated using lightly doped drain-source (LDD) regions. The LDD structure is comprised of a shallow, gate-aligned n.sup.- or p.sup.- region formed between the MOSFET channel and the respective n.sup.+ or p.sup.+ source and drain diffusions. This structure increases breakdown voltage and reduces impact ionization and hot electron emission by spreading the high electric field at the drain pinchoff region into the n.sup.- region.
One method of fabricating LDD structures involves the use of sidewall spacers in conjunction with etching techniques such as anisotrophic and reactive ion etching (RIE). Tsang et al., "Fabrication of High Performance LDDFET'S with Oxide Sidewall-Spacer Technology", IEEE Transactions on Electron Devices, Vol. Ed-29, No. 4, April, 1982, pp 590-596, teaches a method for forming an LDD NMOSFET. According to Tsang et al., after forming the polysilicon gate structure consisting of the gate oxide, the polysilicon gate and an oxide etch mask n-type ions are implanted to form the n.sup.- LDD regions A layer of chemical vapor deposited (CVD) silicon dioxide of a desired thickness is then conformally deposited and, using directional RIE, the planar portion of the CVD oxide is removed to leave the vertical oxide sidewall spacer on the polysilicon gate structure. The sidewall spacer is used as a mask during arsenic ion implantation of the n.sup.+ source and drain regions.
The Tsang et al. process, however, would not appear to be suitable for selective deposition of refractory metals, in that the process used to remove the oxide mask and expose the gate electrode would inherently remove material regions of the sidewall oxide. The device would then be prone to the shorting problems discussed above.
Liu, U.S. Pat. No. 4,330,931 issued May 25, 1982, discloses a process for forming a self-aligned silicon gate NMOS FET having n.sup.- source and drain extensions. In this process, after forming a polysilicon gate having a nitride overhang mask, arsenic ions are implanted to form the n.sup.+ source and drain. During the implant step, lightly doped source and drain extensions are also formed due to the blocking of some ions by the nitride overhands. The structure is then subjected to a high temperature oxidization step to grow a 100 nanometer thick oxide over the sides of the polysilicon gate and the substrate corresponding to the source and drain regions. The oxide thus formed over the n.sup.+ source and drain regions is then damaged by argon ion implantation. During this oxide damaging step, the oxide over the n.sup.- source and drain extensions regions at the sidewalls of the gate is protected by the nitride overhang mask. The damaged oxide and the nitride mask are then removed and a tungsten layer is selectively deposited over the exposed n.sup.+ source and drain regions and the gate.
The oxide damaging step of the Liu '931 process is not only an extra process step but also requires very careful control. Furthermore, any variation in undercutting the polysilicon may cause damage to the sidewall oxide during the argon ion bombardment step. The Liu '931 process also appears to be limited to forming a very thin, 100 nanometers thick, polysilicon gate sidewall oxide. Consequently, upon selective deposition of tungsten over the polysilicon gate and the source and drain areas, adjacent tungsten strips still may short due to tungsten bridging.
Jecmen, U.S. Pat. No. 4,198,250 issued Apr. 15, 1980, also used an overhang mask on the polycrystalline silicon gate electrode to effect the implanting of an LDD structure. In this case, the mask is silicon dioxide. The overhang mask is provided by wet chemical overetching of the supporting poly gate, then the n.sup.+ source and drain regions are implanted. During implantation, the mask overhang absorbs a large percentage, but not all, of the incident implant species. As a consequence, the n.sup.+ source and drain implant also forms shallow, lightly doped LDD regions beneath the mask overhang between the channel and the n.sup.+ source and drain regions.
As mentioned, overlap between the gate electrode and the source and drain results in parasitic capacitance between the impurity region and the gate, known as Miller capacitance, which decreases high frequency response and operational speeds. Increased depth can also cause increased susceptibility to punch through. The Jecmen '250 patent states that its LDD regions do not diffuse (laterally or vertically) significantly during the subsequent high temperature processing. As a consequence, the LDD regions do not significantly overlap the gate and retain their shallow junction depth. The initial shallow aligned LDD regions and the subsequent dimensional stability provide reduced Miller capacitance.
As indicated by perusal of the above article and patents, the effectiveness of lightly doped source-drain structures and sidewall oxide structures in improving device performance and eliminating problems associated with small geometry high density integrated circuit structures is known. As is also evident from a reading of the above article and patents, in implementing these beneficial structures, it is difficult to avoid process complexity and to maintain device yields. It is accordingly, an object of the present invention to implement a lightly doped drain/source structure using a process of relative simplicity, which is conducive to high yields, and is amenable to the incorporation of other beneficial structures, described below.
In addition, it is an object of the present invention to provide a reproducible manufacturing process for forming a short channel graded source and drain doping profile for controlling hot carrier effects. It is also an object of the present invention to optionally incorporate sidewall oxide spacers into such process with a minimum of additional process steps for the purpose of eliminating shorting between the gate and the source/drain metal depositions.
Chiao, U.S. Pat. No. 4,503,601, issued Mar. 12, 1985, which is assigned to the assignee of the present application, is directed to a reproducible manufacturing process for forming NMOS devices which incorporate both LDD structures and sidewall oxide spacers. Initially, after forming the gate oxide, and forming a doped polysilicon layer, a silicon oxide layer, and a silicon nitride layer and patterning the poly-oxide-nitride into the configuration of the gate electrode, n.sup.- LDD regions are formed in self-alignment with the gate by ion implantation. Then, a low temperature selective oxidation process is applied to form a much thicker layer of oxide on the vertical sidewalls of the highly doped polysilicon gate than over the lightly doped exposed substrate. The thin source/drain oxide is then readily removed, leaving thick sidewall oxide spacers which self-align the n.sup.+ source and drain implants with the LDD regions and also prevent shorting of the gate to the source/drain diffusion during subsequent metallization
It is another object of this invention to modify and extend the Chiao LDD/sidewall oxide structure to incorporate a guard band diffusion into the source and drain structures in combination with either or both the LDD structure or the sidewall oxide structure using a minimum of additional process steps, for the purpose of minimizing effects such as drain-induced barrier lowering and subthreshold leakage in addition to minimizing other, short channel effects and Miller capacitance.
It is yet another object of this invention to realize the above objectives in a process for forming complementary MOS structures.